Instructions in microprocessors are often re-dispatched for execution one or more times due to pipeline errors or data hazards. For example, an instruction may need to be re-dispatched where an instruction refers to a result that has not yet been calculated or retrieved. Because it is not known whether an unpredicted pipeline stall will arise during execution of the instruction, execution of the instruction may lead to runahead operation configured to detect other misses while the initial miss is being resolved.